A Temporal Assertion Extension to Verilog
Journal
2nd International Symposium on Automated Technology for Verification and Analysis(ATVA04)
Pages
499-504
Date Issued
2004-10
Author(s)
Abstract
Many circuit designs need to follow some temporal rules. However, it is hard to express and verify them in the past. Therefore, a temporal assertion extension to Verilog, called Temporal Wizard, is proposed in this paper. It provides several Verilog system tasks for the users to write assertions in testbench directly. Two new concepts, tag and thread, are also introduced so that data can be associated with temporal assertions and provide more functionalities than previous temporal assertion checkers. © Springer-Verlag 2004.
Type
conference paper