Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance
Journal
IEEE Transactions on Microwave Theory and Techniques
Journal Volume
54
Journal Issue
1
Pages
31-38
Date Issued
2006
Author(s)
Abstract
A low insertion-loss single-pole double-throw switch in a standard 0.18-μm complementary metal-oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the P1dB, the body-floating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured P1dB of 21.3 dBm, an insertion loss of 0.7 dB, and an isolation of 35 dB at 2.4 GHz, while at 5.8 GHz, the switch attains a measured P1dB of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB. The effective chip size is only 0.03 mm2. The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches. © 2006 IEEE.
SDGs
Type
conference paper