Clock and Data Recovery Circuit for Optic Fiber Communication

This thesis contains five chapters. The research objective of this thesis is to analyze, design, and implement high-speed CDR circuits for optical fiber receivers that can be readily implemented in an integrated, low-cost, low-power CMOS technology. Our primary contributions to this research include the design methodology and implementation of two CDR circuits fabricated in both CMOS 0.35-μm technologies using linear phase detector (LPD) and binary phase detector (BPD) and we compare and analysis the difference of the two CDR circuits.


Chapter 2, we describe the theorem of clock and data recovery (CDR) circuit. Several architectures and some building blocks of CDR are discussed, including phase detector (PD), frequency detector (FD) for random data, and voltage-controlled-oscillator (VCO).
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The first CDR circuit in CMOS 0.35-μm technology to support a data rate of 1.25-Gb/s is described in Chapter 3. The frequency lock loop (FLL) without a reference clock is integrated in the CDR. We will discuss the architecture of the CDR based on a phase-locked loop. The building blocks for system are discussed. The building blocks are comprised of a two-stage ring oscillator, a linear phase detector (LPD), and a full-rate frequency detector.

Chapter 4 presents the bang-bang CDR fabricated in CMOS 0.35-μm technology to support a data rate from 1050-Mb/s to 1.60-Gb/s with a phase-locked loop (PLL) for frequency acquisition. In this chapter, we also present the analysis of bang-bang loop and some concepts of PLL.

Finally, conclusions and discussions are given in Chapter 5.