A 66-82 GHz VCO with Dual-Tuning and Phase Noise Reduction Techniques in 40 nm CMOS
Journal
2025 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2025 - Proceedings
Start Page
67
End Page
69
ISBN (of the container)
979-833150353-6
Date Issued
2026-02-03
Author(s)
Abstract
This paper proposes a 66-82 GHz voltage-controlled oscillator (VCO) incorporating dual-tuning and phase-noise (PN) reduction techniques. The dual-tuning method enables both coarse and fine tuning, thereby expanding the frequency tuning ratio (FTR) compared to conventional single-band tuning methods. Moreover, both figure of merit (FoM) and the FTR-inclusive FoM (FoMT) are better improved by considering several PN reduction techniques during the design procedure. This chip is fabricated in 40 nm CMOS process, with the core area of 0.079 mm2 and the PDC of 7.8 mW. The FTR is 21.6 %, operating from 65.9 GHz to 81.8 GHz at a supply voltage of 0.8 V. After power calibration, the optimal output power (POUT) is -13.4 dBm, and the PN at the 10 MHz offset is -114.3 dBc/Hz. The FoM and the FoMT are -182.7 dBc/Hz and -189.4 dBc/Hz respectively.
Event(s)
2025 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2025
Subjects
Coarse-Tuning
Dual-Tuning
Fine-Tuning
mm-Wave
Sixth-Generation (6G) Communication
Sub-Terahertz (THz)
VCO
Publisher
IEEE
Type
conference paper