Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation
Journal
VLSI Design
Journal Volume
15
Journal Issue
3
Pages
587-594
Date Issued
2002
Date
2002
Author(s)
Abstract
Delay, power, skew, area and sensitivity are the most important concerns in current clock-tree design. We present in this paper an algorithm for simultaneously optimizing the above objectives by sizing wires and buffers in clock trees. Our algorithm, based on Lagrangian relaxation method, can optimally minimize delay, power and area simultaneously with very low skew and sensitivity. With linear storage overall and linear runtime per iteration, our algorithm is extremely economical, fast and accurate; for example, our algorithm can solve a 6201-wire-segment clock-tree problem using about 1-minute runtime and 1.3-MB memory and still achieve pico-second precision on an IBM RS/6000 workstation.
Subjects
Buffer-sizing; Clock trees; Interconnect optimization; Lagrangian relaxation; VLSI CAD; Wire-sizing
Other Subjects
Algorithms; Application specific integrated circuits; Computer aided design; Computer simulation; Electric power supplies to apparatus; Integrated circuit layout; Interconnection networks; Iterative methods; Lagrange multipliers; Optimization; Bufer sizing; Clock trees; Interconnect optimization; Lagrangian relaxation; Wire sizing; VLSI circuits
Type
journal article
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