Smart Fault-Tolerant Path: A New Path Selection Strategy for Network-on-Chip
Date Issued
2011
Date
2011
Author(s)
Yang, Yu-Kai
Abstract
Networks-on-Chip (NoC) have been proposed to solve increasing scale and complexity of designs in nano-scale VLSI designs. Efficient and deadlock-free routing is critical to the performance of Networks-on-Chip. In this thesis, we proposed an approach, Smart Fault-tolerant Path, can be coupled to any adaptive routing algorithm to improve the performance.
The concept of Smart Fault-tolerant Path is to choose a fault-tolerant channel that will allow the packet to be routed to its destination along a path that is as free as to avoid faulty router when the routing function returns several admissible output channels. In addition to fault-tolerant ability, the proposed selection strategy applied to the Odd-Even routing algorithm outperforms other deterministic and adaptive routing algorithms both in average delay and energy consumption from experimental results.
Subjects
Network on Chip
Fault-Tolerant
SDGs
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-100-R98943099-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):a871ba8aa4988622aa2d15f8cca8cb73