A 10Gbps burst-mode CDR circuit in 0.18μm CMOS
Journal
IEEE Custom Integrated Circuits Conference
Pages
599-602
Date Issued
2006-09
Author(s)
Abstract
A 10Gbps burst-mode clock and data recovery (CDR) circuit has been fabricated in 0.18μm CMOS technology. It recovers the input data and clock within 32 bits by using a gated voltage-controlled oscillator, a quadrature generator and a phase-aligning loop incorporating a half-rate bang-bang phase detector and a digital phase interpolator. The measured peak-to-peak jitter of the recovered clock is 10.44ps. The die area is 1.73 x 2.01 mm2 and draw 200mw from a 1.8v supply. © 2006 IEEE.
SDGs
Type
conference paper