A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique
Journal
Proceedings - IEEE International Symposium on Circuits and Systems
Pages
1423-1426
Date Issued
2011
Author(s)
Abstract
A novel 64-bit hybrid radix-4 sparse-4 tree adder using clock-delayed (CD) footless domino logic is proposed. The adder operates at 6.4GHz with 181ps latency and it consumes 840mW at 1.2V in a standard 90nm CMOS technology. The adder latency is accurately measured by the programmable clock generated from delay-locked loop (DLL). Pseudo-exhaustive testing is applied so that all testable faults in this 64-bit adder are detected by just 23K patterns. This at-speed self testing technique is very useful for speed binning of high performance CPU. © 2011 IEEE.
SDGs
Type
conference paper