Verification of the Low Branch Penalty MIPS Microprocessor
Date Issued
2006
Date
2006
Author(s)
Hu, Min-Kuan
DOI
en-US
Abstract
In modern IC design flow, verification and debugging consume most of the design time. Therefore, it is a good idea to make a verification plan before the design process starts. A verification plan adopts organized and systematic approaches to ensure good quality of the design. A traditional verification plan involves simulation of the design and compares the result with a golden model. However, it suffers from the deficiency in coverage and debugging capability. As the recent verification methodology evolves, various new techniques are proposed. In this thesis we adopted both the traditional approaches and new ones in balance to compensate each other and archive high quality of design.
We conducted our design verification in the Register Transfer Level (RTL). Our objective was to find as many bugs in the RTL as we can so that we may treat it as a golden model for the verification in the later design stages.
The design under verification (DUV) was implemented by Hung Chi Chang as his master thesis in GIEE NTU. We took his thesis as the design specification.
Subjects
驗證
正規驗證
MIPS
verification
formal verification
Type
thesis
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