Divider-Less Clock and Data Recovery Circuit and Multiplying Delay-Locked Loop
Date Issued
2014
Date
2014
Author(s)
Chen, Sheng-Tzung
Abstract
As the development and advancement of modern technology, portable device plays a more and more important role in the communication system. Due to the finite battery capacity, low power consumption becomes an important target to evaluate the performance of circuits. It is our desire to design the circuits featuring outstanding performances.
This thesis is consisted of two parts. In chapter 2, we propose a multiplying delay-locked loop which uses its low-speed reference clock and input buffers to generate the selection signal. The selection signal even provides the divide function to MDLL feedback clock, and the divided clock output compares the phase error with reference clock. In this method, this MDLL can turn off the divider to save 30% power consumption. Its power consumption is 2.26mW from a 1.0V supply. The active area is 0.032mm2.
In chapter 3, an injection-locked clock and data recovery circuit is presented with power detection technique to calibrate the frequency of digital control oscillator and generate the recovered clock. These power detection circuits take the place of reference PLL or other high-speed circuits in conventional CDR circuits, saving great power and area of inductors. The measured BER (bit error rate) is less than 10-12 for a 25 Gb/s PRBS of 27-1. Its power consumption is 24.9mW from a 1.1V supply. The total area is 0.23mm2.
Subjects
時脈與資料回覆電路
倍頻延遲鎖相迴路
Type
thesis
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