1.2 kV 4H-SiC VDMOSFETs with Si-implanted Surface: Performance Enhancement and Reliability Evaluation
Journal
Proceedings of the International Symposium on Power Semiconductor Devices and ICs
Journal Volume
2021-May
Start Page
211
End Page
214
ISBN (of the container)
9784886864222
ISBN
9784886864222
Date Issued
2021-05-30
Author(s)
DOI
10.23919/ISPSD50666.2021.9452284
Abstract
This paper reports on the performance improvement in 1.2KV 4H-SiC VDMOSFETs using a Si-implanted surface technique. Firstly, the devices with Si implantation on the surface shows a decrease of carbon atom percentage from XPS and EDX analysis, an improvement of subthreshold slope (SS) and mobility in n-MOSFETs, and a lower interface state density (DIT) near the conduction band edge from n-MOS capacitors. Secondly, high-voltage VDMOSFETs with Si implantation on the surface shows an improvement in SS, ID, breakdown voltage, and electrical safe operating area (SOA). Finally, the reliability including positive/negative bias temperature instability (PBTI/NBTI) and RON stability under high-voltage pulses are evaluated in high-voltage VDMOSFETs. Therefore, the Si-implanted surface technique is effective in enhancing the performance of 4H-SiC power VDMOSFETs without stability concerns.
Event(s)
33rd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2021, Virtual, Nagoya, 30 May 2021 through 3 June 2021. Code 170861
Publisher
IEEE
Type
conference paper