Improving Property Directed Reachability Techniques for Sequential Equivalence Checking under Retiming and Resynthesis
Date Issued
2014
Date
2014
Author(s)
Hsu, Sheau-Yun
Abstract
Sequential equivalence checking is an important practical problem. Previously, sequential equivalence checking problems are either treated as general property checking problems or solved by finding an inductive set of internal equivalent signals. However, difficulties are encountered by either approach. In this thesis, we study several related techniques and derive a hybrid method that allows a property checking engine to utilize functionally equivalent signals to prove the equivalence of both circuits. Our method shows a bridge between very different approaches.
Subjects
循序電路等效驗證
性質導向可達度
時序重置
布林可滿足性問題
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-103-R01943081-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):da5da1b60a295a9b5cc9973fecc0d74b