Design of High-Speed Energy-Efficient Successive-Approximation Register Analog-to-Digital Converters
Date Issued
2014
Date
2014
Author(s)
Chang, Ting-Kai
Abstract
This dissertation proposes two circuit design techniques for high-speed energy-efficient successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the proof-and-concept prototypes, the proposed techniques are able ti improve the operating speed and decrease total circuit power consumption. The proposed techniques and chip measurement results are sketched as follows:
The first technique is using charge-sharing method to achieve a Pipelined SAR ADC, this architecture using passive components capacitors for second stage sampling without using OP amplifiers, so the power consumption can be decreased greatly. A 9-bit 100MS/s SAR ADC with proposed method is implemented in TSMC 90nm 1P9M CMOS technology. As for measurement results, 1MHz input sinusoidal signal is fed into the ADC, when the operating frequency at 10MS/s, 20MS/s, 50MS/s and 100MS/s, the ENOB of ADC are 7.33 bits, 7.27 bits, 6.92 bits and 6.57 bits. The ADC consumes 2.2mW from a 1-V supply when the operating frequency at 100MS/s, the resulting figure of merit (FOM) is 231fJ/conversion-step.
The second technique is adding a for reference to decrease the area of capacitor array, also we using the nature of capacitor that current will lagging the voltage, we make some change at switching, so we can achieve the target voltage without charge redistribution, we call this method “voltage-jumping” method. By using this method, we can not only decrease the capacitor array area by 50%, but also reduce the settling time of second bit. A 10-bit 100MS/s SAR ADC with proposed method is implemented in TSMC 90nm 1P9M CMOS technology. As for measurement results, 1MHz input sinusoidal signal is fed into the ADC, when the operating frequency at 10MS/s, 50MS/s and 100MS/s, the ENOB of ADC are 7.42 bits, 7.57 bits and 7.32 bits. The ADC consumes 1.6mW from a 1-V supply when the operating frequency at 100MS/s, the resulting figure of merit (FOM) is 100fJ/conversion-step.
Subjects
高速
低功率
逐漸趨近式
類比至數位轉換器
Type
thesis
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