Digital Integrated Circuit Design of DC-offset Removal Scheme for Protective Relay
Date Issued
2004
Date
2004
Author(s)
Hong, Pei-Lun
DOI
zh-TW
Abstract
In this thesis, we design a chip to implement DC-offset removal scheme, and then we use FPGA to verify the function of our circuit for proving its availability. By Bottom-Up design style, we divide this system to three parts. First part is FCDFT module, and we adopt Pipeline concept to accomplish it. Second part is complex number computing module, and we develop a “re-normalization” scheme to improve precision. Last part is CORDIC module, and we use it for transferring rectangular coordinate to polar coordinate. About its result, the error rate of baseband amplitude is 1.6~1.9%, phase angle 0.005~0.05%.
If we adopt TSMC 0.35um technology library to synthesis our design, the area is approximately 33242um2, the maximal frequency is 65.32MHz. If we use Altera Stratix EP1S25F780C5 device to implement our design, it use 19% logic element, 87% DSP block and 9% pins, and its maximal frequency is 6.13MHz.
Subjects
全週期傅利葉轉換
座標旋轉數位運算演算法
複數運算
Complex Number Arithmetic
FCDFT
CORDIC Algorithm
Type
thesis
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