JPEG-LS編碼器之交易層級模型及其驗證使用SystemC
Transaction Level Modeling and Verification of JPEG-LS Encoder using SystemC
Date Issued
2007
Date
2007
Author(s)
Chen, Chao-Lun
DOI
zh-TW
Abstract
With the ever-increasing complexity of System-on-Chip, the designer faces great challenges to design a system. So the designer has been searching for new methodology that can handle the complexity with increased productivity and decreased time-to-market. In order to simplify the design flow of an application specific integrated circuit, the system level design issue is getting more important.
SystemC provides a convenient design flow for transaction level modeling and allow the designers create the design of the whole system on a high level stage, and verify the system at the early model, as well as down to the RTL model. Consequently, it can reduce the design cost. In this thesis we present the design flow of transaction level modeling of a JPEG-LS encoder based on SystemC from the algorithm level down to the register transfer level, and compare the diversity of different models. Finally, we verify the system design and performance analysis.
Subjects
SystemC
JPEG-LS
TLM
驗證
編碼器
Verification
encoder
Type
thesis
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