Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits
Date Issued
2012
Date
2012
Author(s)
Kuo, Chun-Yi
Abstract
Through silicon via (TSV) is a widely used interconnect technology in three dimensional integrated circuits (3D ICs). This paper shows that defective TSVs can induce small delay faults in surrounding logic gates. We present simulation results of TSV-induced small delay fault (TSDF) due to mechanical stress or pinhole leakage. A test technique is proposed to detect TSDF using a physical-aware fault extractor and timing-aware ATPG. This technique requires no DfT area overhead and no direct TSV probing. Experimental results on benchmark circuits show that test coverage can be improved by nearly 43% and 20% for stress-induced and leakage-induced TSDF, respectively. In our results, the test length overheads of both TSDF are less than 5%.
Subjects
Through silicon via (TSV)
Small delay defect
Mechanical stress
Pinhole leakage
Type
thesis
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