An All-Digital Clock and Data Recovery Circuit with Bandwidth Calibration

This thesis describes the design and implementation of an all-digital clock and data recovery circuit (ADCDR) with bandwidth calibration for 9.5 gigabit/s operation. The proposed architecture achieves constant jitter transfer bandwidth independent of data transition density. This ADCDR is fabricated in 28-nm CMOS technology. Its active area is 0.065mm2 and the power is 33mW from a supply of 1.05 V. The integrated RMS jitter is 2.25ps for PRBS7.