Thermal-Aware Router-Sharing Architecture for 3D Network-on-Chip Designs
Date Issued
2010
Date
2010
Author(s)
Huang, Yong-Ruei
Abstract
In this thesis, we study 3D Network-on-Chip(NoC) and analyze how thermal impacts degrade its performance. NoC is regarded as a novel solution for System-on-Chip communications, and 3D NoC technology has more advantages than 2D NoC in many aspects. The advantages include higher IP mapping density, lower network latency, higher bandwidth and lower power consumption. However, the power density of 3D NoC is times of 2D NoC, but the thermal conductivity is smaller. Therefore, the overheated problem will be more serious in 3D NoCs. To solve the issue, we propose a router-sharing architecture for 3D NoC which outperforms existing 3D NoC designs under thermal impacts. According to thermal simulations, in conventional designs, the routers on the top layers far from the heat sink have to be disabled frequently to avoid thermal emergency. Therefore, the proposed architecture removes all routers on the top layers and uses only buses to connect top-layer PEs to the routers underneath. At 85 oC, our architecture receives 1.4 times as many packets when compared to conventional designs. If the temperature constraint is set at 80oC, our architecture can receive 2 times as many packets. In addition, this new architecture is energy-efficient because the average number of hops is reduced.
We also study how thermal noise affects circuit reliability. As technology evolves, logic threshold decreases, which makes circuits more sensitive to thermal noise. At the 8nm technology node, if IC temperature reaches 85oC, about one error will occur within four days. If IC temperature reaches 105oC, about five errors will occur in a day, which is unacceptable in terms of circuit reliability. Therefore, the proposed thermal-aware router-sharing architecture would further improve 3D NoC performance in the future.
We also study how thermal noise affects circuit reliability. As technology evolves, logic threshold decreases, which makes circuits more sensitive to thermal noise. At the 8nm technology node, if IC temperature reaches 85oC, about one error will occur within four days. If IC temperature reaches 105oC, about five errors will occur in a day, which is unacceptable in terms of circuit reliability. Therefore, the proposed thermal-aware router-sharing architecture would further improve 3D NoC performance in the future.
Subjects
3D Network-on-chip
network performance analysis
thermal analysis
3D ICs
Type
thesis
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