A 40 Gb/s CMOS Transceiver Chipset for Optical Communication Systems
Date Issued
2005-07-31
Date
2005-07-31
Author(s)
DOI
932213E002109
Abstract
This project utilizes the advanced CMOS
process to develop a 40-Gb/s transceiver for
OC-768/STM-256 standard in synchronous
optical networks (SONET), exploiting the
territory of ultra high-speed and broadband
circuits. Employing new architectures and
circuit topologies, the transceiver consists of a
40-Gb/s 4-to-1 MUX and laser driver, a
40-GHz PLL-based frequency synthesizer, a
40-Gb/s TIA/preamplifier/equalizer, and a
40-Gb/s quarter-rate CDR which automatically
retimes and demultiplexes the full-rate
data into parallel channels. To be fabricated in
0.13- Μ m CMOS technology, the fully
integrated transceiver provides solutions to
issues such as noise, speed, and voltage
headroom in deep sub-micron CMOS process
and contributes to numerous analog and
mixed-signal designs. The duration of this
project is three years and the deliverables
include: (1) design, simulation, fabrication,
and testing of individual building blocks (i.e.,
MUX, laser driver, frequency synthesizer,
TIA, preamplifier, equalizer, and CDR); (2)
mm-wave application and system
optimization; (3) system integration, testing,
and optimization. This project provides
training in broadband and ultra high-speed
circuit design for researchers and students,
creating promising and profitable results for
next generation’s optical communication
system.
Subjects
optical communication
transceiver
MUX
PLL
frequency
synthesizer
synthesizer
TIA
limiting amplifier
CDR
equalizer
Publisher
臺北市：國立臺灣大學電子工程學研究所
Type
report
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