X架構下的全晶片繞線框架
XROUTE: AN X-ARCHITECTURE FULL-CHIP ROUTER BASED ON A NOVEL MULTILEVEL FRAMEWORK
Date Issued
2006
Date
2006
Author(s)
Chang, Chen-Feng
DOI
en-US
Abstract
As nanometer IC technologies advance, the interconnect delay has become a first order effect on chip performance. To handle this effect, the X-architecture has been proposed for high-performance integrated circuits. In this thesis, we present a novel multilevel full-chip routing system using the X-architecture, called XRoute. Unlike the traditional V-cycle multilevel framework that adopts bottom-up coarsening followed by top-down uncoarsening. Our novel multilevel framework works in the inversed V-cycle manner: top-down uncoarsening followed by bottom-up coarsening. The top-down uncoarsening stage performs octagonal global routing and X-detailed routing for local nets at each level and then refines the solution for the next level. Then, the bottom-up coarsening stage performs the X-detailed routing to reroute failed nets and refines the solution level by level. To take full advantage of the X-architecture, we also develop a progressive X-Steiner tree algorithm based on the delaunay triangulation approach for the X-architecture. Compared with the state-of-the-art V-cycle multilevel routing system for the X-architecture [18](DAC-05), experimental results show that our XRoute reduces the respective wirelength and average delay by about 14.05% and 30.62%, with better routing completion.
Subjects
繞線
架構
多階層
X-Architecture
XRoute
Multilevel
Router
Routing
Type
thesis
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