A Spur-Reduction Frequency Synthesizer for DVB-H Receivers
Date Issued
2006
Date
2006
Author(s)
Chen, Hsin-Hua
DOI
en-US
Abstract
The system for fixed and portable reception of digital terrestrial television, known as digital video broadcasting-terrestrial (DVB-T), has been available for several years. Making this available for handheld devices is the next step, along with integration into global system for mobile communications (GSM) is an inevitable trend. In order to support these new applications, a new standard called digital video broadcasting-handheld (DVB-H) has become a popular topic.
Synthesizer design still remains one of the most challenging issues in RF systems because it must meet very stringent requirements such as: settling time, phase noise, reference feedthrough (also called reference spur), etc. Several trade-offs exist in the design of synthesizer. First, the settling time is largely determined by the loop bandwidth which is limited to approximately 1/10 of the reference frequency for loop stability considerations. Second, the phase noise of the oscillator is reduced by the feedback loop only within the loop bandwidth. Finally, in order to suppress the reference spur, a small loop bandwidth is required. To solve all these trade-offs, we have proposed several new architectures adopting the charge conservation and sample-and-hold concepts to achieve a fast locking, wide range, and low reference spur PLL.
Chapter 2 will give basic ideas of phase-locked loops (PLLs) as well as some important characteristics in a frequency synthesizer. A design flow is described along with detailed parameter setting and architecture simulations together with some examples are demonstrated.
Chapter 3 will present our proposed frequency synthesizer which is fabricated in 0.18-um CMOS process. At first, we will discuss the motivation including several design issues, such as: phase noise, switching time, reference spur… Then, analysis and implementation of our circuit are introduced in detail. Finally, we will present the experimental results of this work.
In chapter 4, three new architectures will be proposed to further improve the spur-reduction function. Two main drawbacks of the structure proposed in chapter 3 can be improved greatly. Also, the experimental results will be presented in the end of this chapter.
Finally, chapter 5 will give some conclusions to this work, comparing and contrasting the architectures presented in this paper with other published works. Issues that should be noted for future work on this topic are also discussed.
Subjects
頻率合成器
鎖相迴路
數位電視
frequency synthesizer
PLL
DVB-H
Type
thesis
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