Publication:
A Spread Spectrum Clock Generator For SATA With Programmable Triangular Modulator

dc.contributor曹恆偉zh-TW
dc.contributor臺灣大學:電子工程學研究所zh-TW
dc.contributor.authorChia-Tseng ,Chiangen
dc.creatorChia-Tseng ,Chiangen
dc.date2009en
dc.date.accessioned2010-07-14T07:44:01Z
dc.date.accessioned2018-07-10T01:43:45Z
dc.date.available2010-07-14T07:44:01Z
dc.date.available2018-07-10T01:43:45Z
dc.date.issued2009
dc.description.abstractAs external storage devices are widely used, high-speed serial links connection host and external devices are becoming popular. Serial AT Attachment (SATA.) is one of the most promising technologies providing large bandwidth up to 3Gb/s with possible extension to 6Gb/s in the near future. As operating a high speed data rate, currents and voltages present in the circuit and the signal traces lead to great Electro-Magnetic Interference (EMI), Therefore, SATA systems require a wide spreading of 5000ppm and a 30~33KHz modulation rate to reduce EMI. Spread spectrum is a special frequency modulation technique, which is sacrificed the signal integrity of the clock to reduce the EMI. In this thesis, we proposed a novel spread spectrum clock generator (SSCG) to release the trade-offs between the jitter performance and the amount of EMI reduction for SATA appications. Besides considering the amount of EMI peak reduction in frequency-domain, it is more important to take care of the impact in time-domain for SSCGs since the signal integrity in time-domain is a very significant issue for serial data transmissions. This chip is implemented in the process of 0.18um CMOS. In chapter 4 we proposed a programmable triangular generator technique for SSCG (Down spread 2500ppm~ 5000ppm). The technique utilizes the digital data stored in up/down counter to control the spread spectrum amount. An integer-N frequency synthesizer (low frequency) supplies the up/down counter clock to maintain the modulation frequency. Therefore we can adjust spread spectrum amount dynamically to achieve an optimal value between EMI reduction amount and the performance of jitter.en
dc.description.tableofcontents論文審定書(中文)………………………………………………………………………i文審定書(英文)………………………………………………………………………iii謝………………………………………………………………………………………v文摘要………………………………………………………………………………viibstract…………………………………………………………………………………ix錄……………………………………………………………………………………xi片目錄………………………………………………………………………………xiv格目錄……………………………………………………………………………xviii一章 緒論………………………………………………………………………… 1 1.1 動機………………………………………………………………………… 1 1.2 論文架構…………………………………………………………………… 5二章 展頻時脈產生器之基本觀念……………………………………………… 6 2.1減少電磁干擾效應之技巧……………………………………………… 6 2.2 展頻之基本原理…………………………………………………………… 9 2.2.1 觀念…………………………………………………………………… 9 2.2.2 展頻模式及展頻量………………………………………………… 12 2.2.3 調變頻率……………………………………………………………… 13 2.2.4 調變波形……………………………………………………………… 14 2.2.5 時間域影響…………………………………………………………… 16 2.2.5.1週期至週期時間動……………………………………………… 17 2.2.5.2長時期時間抖動………………………………………………… 18 2.3 使用展頻時脈的考量……………………………………………………… 19 2.4 展頻時脈產生器的調變方式與架構……………………………………… 21三章 使用三角積分調變的分數式頻率合成器………………………………… 25 3.1鎖相迴路的基本原理……………………………………………………… 26 3.2 鎖相迴路的分析…………………………………………………………… 26 3.2.1 相位頻率偵測器與回路濾波器……………………………………… 27 3.2.2 電壓控制振盪器……………………………………………………… 29 3.2.3 鎖相迴路的線性模型………………………………………………… 29 3.2.4 鎖相迴路的相位雜訊………………………………………………… 31 3.3 分數式頻率合成器………………………………………………………… 33 3.3.1 脈波移除……………………………………………………………… 33 3.3.2 小數突波……………………………………………………………… 35 3.4 三角積分調變器…………………………………………………………… 37 3.5 MASH 1-1-1三角積分調變器……………………………………………… 39四章 可程式三角波調變的展頻時脈產生器…………………………………… 43 4.1 展頻時脈產生器在除頻器調變的架構…………………………………… 43 4.1.1 傳統對除頻器做調變的展頻時脈產生器……………………………… 44 4.1.2 所提出可程式三角波調變的展頻時脈產生器……………………… 46 4.2 線性模型與參數設計……………………………………………………… 50 4.2.1 行為模擬………………………………………………………………… 52 4.3 電路組成元件……………………………………………………………… 58 4.3.1可讀出資料的SIPO介面架構…………………………………………59 4.3.1.1 SIPO介面…………………………………………………………60 4.3.1.2 SIPO之Control Logic……………………………………………… 61 4.3.1.3 樹狀解碼器(Tree Decoder)………………………………………62 4.3.2 可程式化的三角波調變器…………………………………………… 63 4.3.2.1 比較器(Comparator)………………………………………………65 4.3.2.2 整數型式頻率合成器………………………………………………66 4.3.3 產生3GHz~2.985GHz的分數式頻率合成器…………………………73 4.3.3.1電荷幫浦電路與偏壓部分…………………………………………73 4.3.3.2 MASH 1-1-1…………………………………………………………74 4.3.3.3三階迴路濾波器……………………………………………………74 4.3.3.4 3GHz的壓控振盪器…………………………………………………75 4.3.3.5預除器(Prescaler)……………………………………………………76 4.4模擬設定與結果………………………………………………………………79 4.4.1可讀出資料的SIPO介面架構………………………………………79 4.4.2可程式化三角波調變器………………………………………………80 4.4.2.1頻率合成器(276MHz~552MHz)…………………………………80 4.4.2.2計數邏輯控制與10位元的上下數計數器………………………82 4.4.3產生3GHz~2.985GHz的分數式頻率合成器…………………………83 4.4.3.1相位頻率偵測器…………………………………………………83 4.4.3.2 3GHz的壓控振盪器………………………………………………84 4.4.3.3未展頻的展頻時脈產生器模擬圖………………………………84 4.4.3.4向下展頻5000ppm的SSCG模擬圖……………………………85 4.4.3.5向下展頻2500ppm的SSCG模擬圖……………………………86 4.4.3.6可程式展頻量的SSCG整體比較………………………………86 4.5 實驗結果………………………………………………………………………87 4.5.1晶片佈局………………………………………………………………88 4.5.2量測環境設定…………………………………………………………89 4.5.3印刷電路板製作………………………………………………………90 4.5.4量測結果………………………………………………………………91 4.5.5量測結果探討…………………………………………………………92五章 總結與展望……………………………………………………………………97 5.1 總結…………………………………………………………………………… 97 5.2 展望…………………………………………………………………………… 98考文獻……………………………………………………………………………… 99en
dc.format.extent4888709 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.otherU0001-0807200917082800en
dc.identifier.urihttp://ntur.lib.ntu.edu.tw//handle/246246/189178
dc.identifier.uri.fulltexthttp://ntur.lib.ntu.edu.tw/bitstream/246246/189178/1/ntu-98-R95943094-1.pdf
dc.languagezh-TWen
dc.language.isoen_US
dc.subjectSpread Spectrum Clock Generatoren
dc.subjectprogrammable triangular generatoren
dc.subjectUp/Down counteren
dc.subjectElectro-Magnetic Interferenceen
dc.subjectinteger-N frequency synthesizeren
dc.titleA Spread Spectrum Clock Generator For SATA With Programmable Triangular Modulatoren
dc.typethesisen
dspace.entity.typePublication

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