A 2 x 25-Gb/s Receiver With 2:5 DMUX for 100-Gb/s Ethernet
Journal
Ieee Journal of Solid-State Circuits
Journal Volume
45
Journal Issue
11
Pages
2421-2432
Date Issued
2010
Author(s)
Wu, Ke-Chung
Abstract
A 2 × 25-Gb/s receiver for 100-Gb Ethernet (100-GbE) has been implemented in 65-nm CMOS technology. A new regulation mechanism is applied to the limiting amplifier to minimize its gain and bandwidth variations. Two low-power full-rate CDRs (with a built-in clock generator) and a high-speed 2:5 DMUX circuit are integrated. Although only two channels are implemented, this receiver provides exactly the same operation as a four-channel one while dealing with independent channels. The prototype achieves bit error rate <10 -12 with 20-mVpp input sensitivity, consuming a total power of 510 mW from a 1.2-V supply. © 2010 IEEE.
Type
journal article