A 12.5fJ/conversion-step 8-bit 800 MS/s Two-Step SAR ADC
Journal
IEEE Transactions on Circuits and Systems II
Journal Volume
63
Journal Issue
12
Pages
8000-8010
Date Issued
2016
Author(s)
Abstract
This brief presents a 0.9-V 8-bit 800-MS/s energy-efficient two-step successive-approximation register (SAR) analog-to-digital converter (ADC) without an inter-stage residue amplifier. A charge-sharing technique is used to avoid large static current consumption of the residue amplifier and to eliminate the distortion caused by insufficient amplifier output headroom. Besides, a self-triggered latch technique not only saves the digital power but also accelerates the conversion speed by reducing the SAR loop loading. The prototype ADC consumes 1.59 mW at 800 MS/s and achieves a Nyquist signal-to-noise and distortion ratio of 45.8 dB in 40-nm CMOS technology. It results in an figure of merit of 12.5 fJ/c.-s. © 2004-2012 IEEE.
Subjects
Analog-to-digital converter (ADC); charge sharing; self-triggered; successive approximation; two-step
SDGs
Other Subjects
Approximation theory; Energy efficiency; Frequency converters; Signal to noise ratio; Analog to digital converters; Charge sharing; self-triggered; Successive approximations; two-step; Analog to digital conversion
Type
journal article