RF FREQUENCY SYNTHESIZER AND ITS BUILDING BLOCKS
Date Issued
2004
Date
2004
Author(s)
Chang, Chia-Chi
DOI
en-US
Abstract
For modern communication system, a stable local oscillation (LO) is an indispensable component. Either optical communication or wireless communication requires a low-noise signal source for the modulation of the transmitted signal. Phase-locked loop (PLL) technique has been developed for decades and is the most frequently adopted to realize a high-quality LO source. This thesis is dedicated to the design of the essential building blocks for a PLL in high frequency, the voltage-controlled oscillator (VCO) and the frequency divider.
A VCO plays the role of signal generation in a PLL system. Its phase noise dominates in the frequency domain outside the loop bandwidth. As many published literatures show, the noise performance degrades as the operation frequency arises. Thus, how to generate high-frequency oscillation with great noise performance becomes an issue of concern. In this thesis, we brought out an effective method capable of raising maximum oscillation frequency with good phase noise. The topology proposed combines the conventional cross-coupled VCO and the push-push architecture and by using standard CMOS 0.25-μm process, a 40-GHz push-push VCO is successfully design and measured. This chip demonstrated -15-dBm output power and about 1.3-GHz tuning range. The phase noise is -83 dBc/Hz at 1-MHz offset.
Other than VCO, the frequency divider is the design bottleneck for high-frequency PLL since the conventional flip-flop based structure is not suitable for high-speed operation. In this thesis, high-speed frequency divider topologies, such as injection-locked frequency divider and regenerative frequency divider, are described. In this thesis, a 60 GHz divide-by-two frequency is designed and fabricated using GaAs 0.15-μm pHEMT process. The circuit is capable of operating in two modes. The bandwidth is 650 MHz and 750 MHz in injection-locked mode and regenerative mode respectively. This topology demonstrates high frequency operation with little power consumption. The design of a regenerative frequency divider is also demonstrated in the thesis. The circuit adopted CMOS 0.13-μm process and capable of wideband and high-speed operation. The simulation results show that this circuit can function from 18 GHz to 46 GHz with 7-dBm input power while the input balun demonstrates 4.5-dB insertion loss.
To manifest the design concern of a fully-integrated PLL, the design of a monolithic PLL for wireless LAN application is presented in the last part of the thesis. From the linear system simulation, each building block is designed to acquire a compromise between versatile tradeoffs. The transistor-level closed-loop simulation demonstrates the stable operation of the designed PLL.
Subjects
frequency divider
PLL
VCO
frequency synthesizer
鎖相迴路
頻率合成器
壓控振盪器
除頻器
Type
thesis
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