Energy-saving techniques for low-power graphics procrssing unit
Journal
2008 International SoC Design Conference, ISOCC 2008
Journal Volume
1
Date Issued
2008
Author(s)
Abstract
This paper presents a graphics processing unit with energy-saving techniques. Several techniques and architectures are proposed to achieve high performance with low power consumption. First of all, low power core pipeline is designed with 2-issue VLIW architecture to reduce power consumption while achieving the processing capability of 400MFLOPS or 800MOPS. In addition, inter/intra adaptive multi-threading scheme can increase the performance by increasing hardware utilization, and the proposed configurable memory array architecture can reduce off-chip memory accessing frequency by caching both input data and output results. Furthermore, for graphics applications, a geometry-content-aware technique called early-rejection-after-transformation is proposed to remove redundant operations for invisible triangles. As for circuit level power reduction, power-aware frequency scaling is proposed to further reduce the power consumption. ©2008 IEEE.
Subjects
Adaptive multi-thread; Component; Configurable memory array; Frequency scaling; Low power GPU; Stream processor; Unified shader
SDGs
Other Subjects
Computer graphics; Computer graphics equipment; Dynamic frequency scaling; Electric power utilization; Energy conservation; Graphics processing unit; Image coding; Memory architecture; Pipeline processing systems; Program processors; Programmable logic controllers; Component; Frequency-scaling; Low Power; Memory array; Multi-thread; Stream processor; Unified shader; Very long instruction word architecture
Type
conference paper