Design of MMIC Broadband Amplifiers and Frequency Doubler
Date Issued
2006
Date
2006
Author(s)
Lee, Wen-Ren
DOI
en-US
Abstract
This thesis includes the design methodology and implementation of a UWB distributed amplifier in TSMC 0.18-μm SiGe BiCMOS HBT process, a 60 GHz Broadband LNA and a high-efficiency K-band balanced frequency doubler both in commercial WIN 0.15-μm PHEMT power process.
The V-band three-stage broadband LNA in chapter 2 demonstrated the measured results of small signal gain about 18 dB from 40 to 70 GHz and noise figure about 6.8 dB at 60 GHz with total dc power consumption of 70 mW. This LNA has the flat gain from 40 to 70 GHz and is designed for the RF front-end amplifier of 60-GHz system.
To enhance the gain and bandwidth performance, the silicon-based HBT low dc power consumption UWB distributed amplifier using the two two-stage cascade configuration and low dc power consumption technique is proposed. The design and analysis of the silicon-based HBT low dc power consumption UWB distributed amplifier are included. The SiGe HBT low-power consumption distributed amplifier presents good gain and bandwidth and demonstrates the highest gain bandwidth product GBW per dc power for broadband amplifiers using silicon-based HBT processes compared with recently published results. Furthermore, the low-power consumption technique can be used to design the wideband low-noise CMOS transimpedance amplifiers. Besides, the measured results of silicon-based HBT low-power consumption UWB distributed amplifier also show wide bandwidth and flat gain from 1.2 to 11 GHz. The dc power consumption is 5.6 mW and suitable for UWB system compared with those of PHEMT devices. The low dc power consumption technique is also proposed to solve the problem of the undesired voltage drop in the distributed structure.
In addition to the UWB amplifier design, a millimeter-wave frequency multiplier, which is widely used for the modulation of high-speed data transmitted at microwave or millimeter-wave carrier frequencies, is also designed in chapter 4. By using the high speed offered by PHEMT technology, the employment of a direct LO chain can reduce mixing circuit phase noise by eliminating a high frequency local oscillator source. Besides, an additional reflector and buffer amplifier would also improve the conversion efficiency and provide enough output power for the mixing circuits. The conversion gain of the PHEMT balanced frequency doubler is greater than 8 dB with output LO power higher than 15 dBm. In addition, we also calculated the PAE in the frequency multiplier, which is better than 10% from 6 to 10 GHz in this design. The measured performance of the PHEMT frequency doubler rivals those of the other reported frequency multipliers.
Subjects
寬頻放大器
頻率倍頻器
amplifier
frequency doubler
Type
thesis
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