Circuit Designs for 40-Gb/s High-Speed Communication Systems
Date Issued
2006
Date
2006
Author(s)
Chien, Jun-Chau
DOI
en-US
Abstract
As the demands for broadband communication continue to expand, the development of high-speed data link has attracted great attention. Recently, several transceivers ICs have been implemented in III-V compound semiconductor and SiGe BiCMOS process for data rate ranging from 10 to 40 Gb/s due to their superior device performance. However, it still remains a challenge for such transceivers to be integrated in a standard CMOS process. Consequently, this thesis describes the major limitations of the CMOS process for the individual building blocks, then presents several novel circuit techniques to reach the speed or bandwidth requirements for the system designs. First, a 40-GHz wideband VCO is demonstrated in a standard 0.18-um CMOS technology. In order to achieve wide tuning range at millimeter-wave frequencies, a non-uniform standing-wave VCO with switched-transmission line architecture is proposed. By switching the length of the transmission lines, a frequency tuning range of 7.5 GHz is achieved by the 40-GHz VCO while maintaining a phase noise better than -96 dBc/Hz at 1-MHz offset. Secondly, the locking ranges of the injection-locked ring oscillators are investigated. To improve the injection efficiency and the locking range for superharmonic frequency division, a multiple-injection technique is proposed. Using a 0.18-um CMOS process, a wideband frequency divider based on a three-stage ring oscillator is implemented for demonstration. With a tunable free-running frequency, the fabricated circuit provides 2:1 and 4:1 frequency division with a single-ended input signal ranging from 13 to 25 and 30 to 45 GHz, respectively. Compared with the case for a single-ended injection, the locking range of the frequency divider almost doubles when multiple input injections with optimum phases are utilized. The experimental results exhibit good agreement with the theoretical derivation and the circuit simulation. Finally, a high-speed 1:2 demultiplexer (DEMUX) implemented in a 0.18-um CMOS process is presented. By employing a distributed architecture for the current-mode-logic latches, a significant speed improvement is achieved in the proposed DEMUX circuit. Provided a 223-1 pseudo-random bit sequence from the pattern generator, the fabricated circuit operates at an input data rate up to 20 Gb/s. The fully integrated DEMUX consumes a dc power of 150 mW from a 2-V supply voltage.
Subjects
壓控振當器
除頻器
解多工器
High-speed communication system
voltage-controlled oscillator
frequency divider
demultiplexer
Type
thesis