Research of 3-D Dual-Radial Power Combining Technique
Date Issued
2015
Date
2015
Author(s)
Yeh, Jin-Fu
Abstract
The research on the development of on-chip power combining techniques is presented this dissertation. For the first time, an innovative 3-D dual-radial PA architecture is proposed. It provides design freedom of impedance selection of power device in TF-based mm-wave PA design. This idea also makes distinguished breakthrough to the traditional 2-D PA architecture without compromising symmetry and compact size of layout. This technique presents not only a power combiner but a new PA architecture. By taking advantage of the dual-radial architecture, the power splitting network and power combining network can share the same active area to complete the fully integration with symmetry layout. This new technique also possesses the impedance freedom to make its feasibility from mm-wave frequency band to microwave frequency band. To demonstrates the feasibility of the proposed 3-D dual-radial PA architecture. Various 3-D PAs have been successfully implemented in different frequency application and in different CMOS process. In terms of mm-wave 3-D PA, a 4-way 60-GHz 3-D PA and 8-way balanced 3-D PA are demonstrated not only the high output power but also high PAD performance. The 4-way 60-GHz PA is also the first mm-wave PA equipped with impedance compensation mechanism for multi-power operation. The 8-way balanced 3-D PA demonstrates the highest 60-GHz output power of 23 dBm in CMOS technology. The chip area of 8-way 60-GHz PA is only 0.72 mm2. In terms of microwave 3-D PA, a bowtie dual-radial architecture is proposed to mitigate the inherent feedback capacitor existing in the original dual-radial PA architecture for unconditional stability consideration. This idea is realized in 24-GHz and 5-GHz PA. The 4-way 3-D bowtie radial PA can achieves highest Pout of 26.1 dBm and high PAD of 635 mW/mm2. Furthermore, the proposed 3-D PA architecture is also adopted to implement a half-watt and one-watt 5-GHz PA in 180-nm CMOS. The proposed fully integrated 5-GHz PA can achieve Pout of 29.5 dBm in cost effective 180-nm CMOS with only 3.33 mm2. A 60-GHz power amplifier utilizing the pre-distortion linearizer was demonstrated at last. The proposed linearization technique can significantly improve IMD3 distortion over 30 dBc at 60-GHz. This technique is valid to cover the wide bandwidth form 57 GHz to 66 GHz. The performances of IP1dB of the 60-GHz PA can be extended around 7 dB and the corresponding OP1dB can be boosted 3 dB in average by enabling the proposed linearization technique.
Subjects
3D PA architecture
CMOS
folded-transformer
radial power distribution network
radial combining network
multi-mode operation
Type
thesis
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