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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Loop latency reduction technique for all-digital clock and data recovery circuits
Details
Loop latency reduction technique for all-digital clock and data recovery circuits
Journal
IEEE Asian Solid-State Circuits Conference
Pages
309-312
Date Issued
2009-11
Author(s)
I-Fong Chen
Rong-Jyi Yang
SHEN-IUAN LIU
DOI
10.1109/ASSCC.2009.5357247
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/352094
SDGs
[SDGs]SDG7
Type
conference paper
