Design of 56 Gb/s NRZ and PAM4 SerDes transceivers in CMOS technologies
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
50
Journal Issue
9
Pages
2061-2073
Date Issued
2015
Author(s)
Abstract
This paper presents two ultra-high-speed SerDes dedicated for PAM4 and NRZ data. The PAM4 TX incorporates an output driver with 3-tap FFE and adjustable weighting to deliver clean outputs at 4 levels, and the PAM4 RX employs a purely linear full-rate CDR and CTLE/1-tap DFE combination to recover and demultiplex the data. NRZ TX includes a tree-structure MUX with built-in PLL and phase aligner. NRZ RX adopts linear PD with special vernier technique to handle the 56 Gb/s input data. All chips have been verified in silicon with reasonable performance, providing prospective design examples for next-generation 400 GbE.
SDGs
Type
journal article