Modeling of MOSFET Devices : capacitance behavior analysis and gate tunneling current model
Date Issued
2006
Date
2006
Author(s)
Lin, Chia-Hung
DOI
zh-TW
Abstract
The thesis analyzes the capacitance behavior and gate tunneling current model of MOS devices. Chapter 1 introduces the importance of high-k materials applied to gate dielectrics. Chapter 2 discusses the gate capacitances behavior of nanometer FD SOI CMOS devices with HfO2 high-k gate dielectric considering vertical and fringing displacement effects using 2D simulation. Based on the 2D simulation results, a unique two-step CS(D)G/CGS versus VG curve could be identified for the device with the 1.5nm HfO2 gate dielectric due to the vertical and fringing displacement effects. Chapter 3 derives the partitoned gate tunneling current model for NMOS devices with an ultra-thin（1nm） gate oxide considering the distributed effects. As verified by the experimentally measured data, this partitioned gate tunneling current model based on the three segment approach provides an accurate prediction of the gate current for the device with a long or short channel. Chapter 4 is the conclusion of this research.
Subjects
電容
穿遂電流
SOI
capacitance
tunneling
Type
thesis
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