A Digital Phase-Locked Loop with Background Supply Noise Cancellation
Journal
2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings
Date Issued
2021
Author(s)
Abstract
A digital phase-locked loop (DPLL) with background supply noise cancellation is presented. By using a digital low-dropout regulator and a supply noise cancellation controller, this DPLL can tolerate a supply noise of 150mVPP. The DPLL is fabricated in 40-nm CMOS technology. Its active area is 0.0195mm2 and the total power consumption is 7.23mW from a supply of 1.1V. The minimum measured supply voltage sensitivity of the digitally-controlled oscillator is less than 0.0261 [%-fDCO/%-VDD]. With a 100kHz, 150mVPP sinusoidal supply noise, the measured rms jitter of the DPLL at 2.4GHz is reduced from 56.38ps to 15.72 ps. © 2021 IEEE.
Subjects
digital low dropout regulator
digital phase-locked loop
digitally-controlled oscillator
jitter
supply noise cancellation
Electric current regulators
Spurious signal noise
VLSI circuits
Voltage regulators
CMOS technology
Digital phase locked loops
Digitally controlled oscillators
Low dropout regulator
Sinusoidal supply
Supply noise
Supply voltages
Total power consumption
Phase locked loops
Type
conference paper