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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
A Compact Threshold Voltage Model for Gate Misalignment Effect of DG FD SOI nMOS Devices Considering Fringing Electric Field Effects
Details
A Compact Threshold Voltage Model for Gate Misalignment Effect of DG FD SOI nMOS Devices Considering Fringing Electric Field Effects
Date Issued
2004-07-31
Date
2004-07-31
Author(s)
郭正邦
DOI
922218E002029
URI
http://ntur.lib.ntu.edu.tw//handle/246246/20015
Publisher
臺北市：國立臺灣大學電子工程學研究所
Type
report
File(s)
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Name
922218E002029.pdf
Size
756.47 KB
Format
Adobe PDF
Checksum
(MD5):05cf1d883aaf9d299efc8b24f32cc05a
