System-Level Performance/Power Evaluation Framework for SoC
Date Issued
2005
Date
2005
Author(s)
Huang, Chin-Chieh
DOI
en-US
Abstract
With the improvement of semiconductor technology, it is now possible that we could construct the whole system on a single chip (SoC). SoC can reduce overall system cost, increase performance, lower power consumption, and reduce chip size. But it also increases the sys-tem design complexity. To facilitate early design space exploration for platform SoC, we are currently developing a system-level performance/power evaluation framework. A platform-
based SoC contains a microprocessor, memory hierarchy, interconnected buses, peripherals,and a set of IP cores. For a platform SoC designer, it is challenging to determine platform components in view of performance and power at the early stage of the design °ow. The proposed system-level simulation framework provides cycle-accurate performance and power evaluation at the system-level through e±cient hardware-software co-simulation.
Subjects
系統單晶片
效能
功率
複雜度
微處理器
記憶體結構
矽智財
系統級
軟硬體共同模擬
system on a single chip (SoC)
performance
power
complexity
microprocessor
memory hierarchy
IP cores
system-level
hardware-software co-simulation
Type
thesis
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