The IC design of a Long BCH code
Date Issued
2005
Date
2005
Author(s)
Chang, Che-Wei
DOI
en-US
Abstract
In new-generation Flash memories, issues such as disturbs and data retention become more and more critical as a consequence of reduced cell size, and hence it will decrease the reliability of memories. Then, the research of error control coding becomes very important.
There are already some researchs of the hardware design of error correcting code in storage equipments. BCH and RS codes form the core of the most powerful known algebraic codes and are widely used .In this thesis, we focus on the encoder/decoder design of BCH(8191,8087,t=8) code under the condition that the error probabily of all bits are independent due to interleaver operation. We integrate various advanced architecture in our system. The parallel architecture is used to syndrome block and Chien search block in order to reduce system’s clock cycles. Modified Euclidean algorithm is chosen to solve the key equation. And group matching algorithm is to minimize the complexity of the multipliers in Chien search architecture. Finally, the encoder/decoder architecture will be confirmed and simulated by XilinxFPGA.
Subjects
碼
設計
硬體
BCH
code
IC
Type
thesis
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