A Quantization Noise Suppression Technique for All-Digital Fractional-N PLLs

This thesis presents a quantization noise suppression technique for all-digital fractional-N PLL to address the quantization noise and fractional spur issues from the ΔΣ modulator. The proposed technique builds a new modulation path that allows the quantization step and modulation frequency to be designed independently and not limited by the loop parameters. The quantization noise power is thus reduced and shifted to higher frequency offset. In addition, by increasing modulator input value and compensating later in digital domain, the fractional spur is also shifted to higher frequency offset. Therefore, both quantization noise and fractional spur are filtered by the loop more effectively.
The proposed technique is implemented in the design of a 3.6-GHz ADPLL. Fabricated in the TSMC 90-nm CMOS technology, the whole system dissipates 9.48 mA from a 1.2-V supply. At 3.6 GHz, the reference spur at 25 MHz offset is -70 dBc and the phase noise measured at 10-MHz offset is reduced from -90 dBc/Hz to -121 dBc/Hz. The fractional spur is also reduced by 5 dB.