A Parallel Simulation Technique for Test Clock Domain optimization to Reduce Peak IR Drop During Scan
Date Issued
2011
Date
2011
Author(s)
Huang, Yu-Chiuan
Abstract
Test clock domain optimization has been shown to be an effective technique to reduce the power supply IR drop during scan chain shifting. However, finding the flip-flop of peak IR drop remains a difficult job because we need to solve millions of linear equations. This thesis presents a new TCDO algorithm that directly changes flip-flops where peak IR drop occurs. A massive parallel algorithm using graphic processor unit (GPU) is adopted to speed up the IR-drop calculation during optimization. The experimental data on large benchmark circuits show that peak IR drop values are reduced by 49% on the average compared with circuits before optimization. Our proposed technique quickly optimizes a half million gate design within 2 hours.
Subjects
peak IR drop
parallel IR-drop simulator
test clock domain optimization
design for testability
Type
thesis
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ntu-100-R98943146-1.pdf
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