An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique

A digital phase-locked loop (DPLL) using the proposed adaptive loop gain controller (ALGC) is presented. The ALGC uses a spectrum-balancing technique to detect the difference of the high-frequency and the low-frequency powers of the bang-bang phase-frequency detector output. Then, the loop gain of the DPLL is adjusted to minimize the output root-mean-square (RMS) jitter. This DPLL is fabricated in 40-nm CMOS process and its active area is 0.016mm2. Operating at a frequency of 3.2 GHz, the power consumption of the DPLL is 1.5mW from a 1V supply voltage. ? 2021 IEEE.