A 40-GHz fast-locked all-digital phase-locked loop using a modified bang-bang algorithm
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
58
Journal Issue
6
Pages
321-325
Date Issued
2011-06
Author(s)
Chao-Ching Hung
Abstract
A 40-GHz fast-locked all-digital phase-locked loop (ADPLL) using a modified bang-bang algorithm is presented. An inductor is used to extend the frequency tuning range of a 40-GHz digitally controlled oscillator. This ADPLL is fabricated by a 90-nm complementary metaloxidesemiconductor process. The measured peak-to-peak jitter and the root-mean-square jitter are 2.622 ps and 303.632 fs, respectively, at 40 GHz. The measured locked times are 1.3 ms and 15 μ without and with the modified bang-bang algorithm, respectively. © 2011 IEEE.
Subjects
All digital; digitally controlled oscillator (DCO); fast locked; phase-locked loop (PLL)
Other Subjects
Jitter; All digital; All digital phase locked loop; Digitally controlled oscillators; fast locked; Frequency tuning range; Peak-to-peak jitter; Phase Locked Loop (PLL); Root mean square jitter; Phase locked loops
Type
journal article