MARS-a RISC-based architecture for LISP
Resource
Tools for Artificial Intelligence, 1989. Architectures, Languages and Algorithms. IEEE International Workshop on
Journal
Tools for Artificial Intelligence, 1989. Architectures, Languages and Algorithms. IEEE International Workshop on
Pages
-
Date Issued
1989-10
Date
1989-10
Author(s)
DOI
N/A
Abstract
A RISC (reduced instruction set computer)-based chip set architecture for Lisp is presented which contains an instruction fetch unit (IFU) and three processing units: integer processing unit (IPU), floating-point processing unit (FPU), and list processing unit (LPU). The IFU feeds instructions to the processing units and provides the branch handle mechanism to reduce branch penalty; the IPU is optimized for integer operations, string manipulation, operand address calculations, and some cooperation affairs for constructing a multiprocessor architecture; the FPU handles the floating point data type, which conforms to IEEE standard 754; and the LPU handles Lisp runtime environment, dynamic type checking, and fast list access. In this architecture, the critical path of complex register file access and ALU (arithmetic and logic unit) operation is distributed into LPU and IPU, and the tracing of a list can be done quickly by the nondelayed car or cdr instructions of LPU. In addition, by using a new branch control mechanism (called branch peephole), this architecture can achieve almost-zero-delay branch and super-zero-delay jump. Performance simulation shows that this architecture would be about 4.1 times faster that SPUR and about 2.2 times faster than MIPS-X.
SDGs
Other Subjects
Artificial Intelligence; Computer Programming Languages--LISP; Almost-Zero-Delay Branch; Floating-Point Processing Unit; Instruction Fetch Unit; Integer Processing Unit; List Processing Unit; RISC-Based Architecture; Computer Architecture
Type
conference paper
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