An MSB-First Asynchronous Add-Compare-Select Unit
Date Issued
2009
Date
2009
Author(s)
Chen, Sheng-Yao
Abstract
As the advance in the technology, chips have become larger and larger, and it becomes more difficult for synchronous design, particularly as clocks get faster. The problems of clock distribution and clock skew minimization are becoming increasingly significant as the technology scales. Besides, the tasks performed on parts of a chip that are close together finish well before a cycle but can’t move on until the next clock cycle. To cope with this problem, some studies have proposed asynchronous design styles.In this thesis, we present a new Add-Compare-Select unit for Viterbi Decoders implemented with a 1-of-N asynchronous single track template. The Viterbi decoder is mainly restricted by the performance bottleneck – the ACS unit. If we can improve the performance of ACS unit, the performance of Viterbi decoder can be sped up, too. By adopting carry-save addition and most-significant-bit-first (MSB-First) comparison, we can fully utilize the advantages of asynchronous circuit so that the computation speed can vary with different input data patterns. We also analyze the expected performance given that every data pattern has the same probability of occurrence. Under that assumption, we can prove that the word length would not affect the performance of our design. A comparison between different circuit styles is also provided, which shows the performance of our design is potentially better than other designs. By constant field scaling, it can be seen that our design has 88.6% improvement in throughput when comparing with static CMOS design. It even has 18.5% improvement in throughput when comparing with fastest state-of-art self-resetting CMOS circuit style. In hardware implementation, our ACS unit and test circuit design are implemented in TSMC 0.18-μm CMOS process. The die size is 1.278mm x 1.018mm giving a total area of 1.30 mm2.
Subjects
Asynchronous design
Single-Track Full-Buffer circuits
MSB-First comparison
Carry-save addition
Add-Compare-Select unit
Type
thesis
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