The Design Method & At-speed Test Technique for Adders, and Wire & Wireless Front-end Transceivers
Date Issued
2012
Date
2012
Author(s)
Wang, Yu-Shun
Abstract
This dissertation presents one of the tops in microprocessor design and communication design between chips. Two parts are discussed: (1) the design methodology and at-speed test technique for high-performance adders, (2) wire and wireless frontend transceivers. The adder, which directly affects the overall performance, is the most important unit in the microprocessors.
This dissertation discusses two aspects of adder design:(1) In deep sub-micron technology, interconnect wire delay will be the bottleneck for high performance adders instead of gate loading. Therefore, reducing interconnect wire delay is important to improve adder performance. (2) At-speed testing detects transition faults. But in the past, only function testing is applied to adder testing. It cannot be used to validate the operating frequency and latency in real silicon.
In the dissertation, we discuss how to design an adder and how to test an adder efficiently: (1) this dissertation shows that the effect of interconnect wire delay will increase in deep sub-micro technology between 0.35-um, 0.18-um, and 90-nm technologies. Therefore, this dissertation uses a new design methodology of 64-bit hybrid radix-4 sparse-4 tree with 181-ps latency, which is faster than the one based on conventional topology. Moreover, by using clock-delayed (CD) footless domino logics, the proposed adder achieves the 6.4-GHz operating frequency in a 90-nm CMOS technology. This design methodology can also be used in high-order adders (>32-bit). (2) This dissertation is the first case using the pseudo-exhaustive testing (PET) for high-speed high-order adders. The at-speed pseudo-exhaustive testing guarantees 100% coverage by only 54K patterns for single stack-at faults. With the delay-locked loop (DLL) latency-measurement technique, speed binning of high performance CPUs is now possible.
However, after improving the microprocessor performance, the chip communication cannot achieve corresponding high speed. Thus, this dissertation discusses two important aspects of communications: (1) With the popularity of the media technology, high speed chip-to-chip transceivers are the critical circuitry in many systems such as USB 3.0 (5 Gbps) and HDMI 1.4 (3.5 Gbps). Moreover, for the mobile applications, low power consumption is also an important factor. (2) The convenience comes with the wireless technology has drastically changed the way people communicate. Other than cellular phone services, the wireless data communication has attracted great attention in recent years. In the transceiver design of a wireless LAN system, the front-end receiver must provide sufficient signal amplification and linearity while maintain minimum noise to ensure the quality of the received signal.
In this dissertation, we discuss the design of the wire and wireless communication technique: (1) This dissertation describes a low-power and high-speed chip-to-chip communication for high density interconnects. A 12-Gb/s front-end transceiver is demonstrated through a wire-bonded AC coupled interconnect (ACCI) channel with 75-fF coupling capacitors, across 10-cm FR4 micro-strip lines. (2) This dissertation also presents a two-stage linearity-enhancement technique in the wireless front-end receiver. The linearization technique integrate single-to-differential and current-reused architecture to achieve high linearity and high gain.
Subjects
adder
wire delay
pseudo-exhaustive testing
at-speed testing
speed binning
AC coupled
front-end receiver
single-to-differential
Type
thesis
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