Simultaneous Test Data Volume and Test Application Time Reduction for System-on-Chip
Date Issued
2007
Date
2007
Author(s)
Bai, Bing-Chuan
DOI
en-US
Abstract
This thesis presents a novel technique to simultaneously reduce the test data volume and test application time for System-on-Chip. The technique includes two-level hardware architecture and the compression algorithm for deterministic test data. The two-level hardware is inserted into the SOC without modifying the embedded cores. The first level, also called L1, is for the entire SOC. The second level, also called L2, is for every individual IP or core in the SOC. L1 compression is achieved by linear-feedback shift register (LFSR) reseeding. L2 compression is achieved by broadcasting test data to multiple cores. L1 compression reduces test data volume only, and L2 compression reduces test data volume as well as test application time. The experimental results on the d695 SOC shows that 79% of original test data volume is reduced, and 39% of original test application time is reduced.
Subjects
電腦輔助設計
積體電路測試
可測試性設計
系統晶片測試
測試資料壓縮
測試時間縮減
Computer-aided Design
VLSI Testing
Test Compression
SOC Testing
Test data compression
test time reduction
Design for testability
Type
thesis
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