Low Power and High Speed 64-bit Domino Logic Adder and AC Coupled Transceiver System
Date Issued
2009
Date
2009
Author(s)
Liu, Chia-Ming
Abstract
With the continuous expansion in digital information, microprocessor plays a more important role in this world than before. In microprocessor, ALU is a key component does all the information processing. In this work, an arithmetic logic system architecture which includes a high performance adder unit and the I/O interface has been proposed.n this work, a 64-bit address generation unit designed for 5.4-GHz and with 185ps latency operation in 1.2-V UMC 90-nm technology is proposed. This adder utilizes three complex domino logics stages with lower stage logic effort and well arranged interconnect routing type and thus improving 70% cross couple capacitance. Moreover, it uses Multi-Vt method to reduce power consumption. And the testing circuit is designed to providing an efficient way to estimate the performance of the adder under different conditions is proposed here too. The adder dissipates 42mW and the core area is 200μm *900μm. low-power high-speed I/O interfaced circuit name by AC Coupled Interconnect targeting for data transmission between two operation units is proposed. The circuit uses low-swing pulse signals and the voltage mode driver to reduce power consumption. Using this receiver, 6Gb/s chip-to-chip communication is demonstrated through wire-bonded ACCI channel with 74fF coupling capacitors, across 10-cm FR4 couple microstrip lines. The chip was fabricated in TSMC 0.18-μm technology. The driver and receiver dissipate 13.5mW and it can achieve error-free operation with 6Gb/s 215-1 PRBS data over 10-cm FR4 channels.
Subjects
adders
domino logics
high-speed integrated circuits
logic effort
AC coupled interconnect
capacitive coupling
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-98-R96943152-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):9a73615b80ebf24f69e8ee8d8abc9676