Optimization of Block Level Chip Verification
Date Issued
2009
Date
2009
Author(s)
Liu, Yen-Po
Abstract
IC verification plays an important role in the design flow and becomes a difficult work with the rising complexity of modern IC designs. Among all methods, equivalence checking is a commonly adopted approaching in IC verification. However, checking the equivalence of a system-level model and RTL design is a major challenge, since the system-level model is written in high level statement, while RTL model is written in the low level description, the challenges can only be overcome with a combination of bit-level and word-level reasoning techniques. For the system-level model, it’s need to translate to the word-level or bit-level representation and check the functionally of both RTL model and system-level model. Another equivalence checking approach, it’s usually combined those RTL model and system-level model in the word-level or bit level representation into a circuit. We use the SAT engine to solve the equivalence problem.n this disquisition, we had discussed the relationship between the system-level model and bit-level representation, and difference architecture of the bit-level implementation cause different performance.
Subjects
Verification
multiplier
equivalent checking
symbolic simulation
formal verification
Type
thesis
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ntu-98-R96943106-1.pdf
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