Annotated Memory References: A Mechanism for Informed Cache Management.
Journal
Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31 - September 3, 1999, Proceedings
Pages
1251-1254
Date Issued
1999
Author(s)
Abstract
As the importance of cache performance increases, allowing software to assist in cache management decisions becomes an attractive alternative. This paper focuses primarily on a mechanism for software to convey information to the memory hierarchy. We introduce a single instruction - called TAG - that can annotate subsequent memory references with a number of bits, thus avoiding major modifications to the instruction set. Simulation results show that annotating all memory reference instructions in the SPEC95 benchmarks increases execution time between 0% and 2% for both statically and dynamically scheduleded processors. We show that exposing cache management mechanisms to software can decrease the execution time of three media benchmarks (epic, pegwit, ijpeg) between 11% and 17% speedups on a 4-issue dynamically scheduled processor. © Springer-Verlag Berlin Heidelberg 1999.
Other Subjects
Parallel processing systems; Cache management; Cache performance; Dynamically-scheduled processor; Instruction set; Memory hierarchy; Memory reference instructions; Memory references; Cache memory
Type
conference paper