Design of CMOS Low-Noise Amplifier for Wireless LAN Applications

Abstract

The convenience introduced by the wireless technology has drastically changed the way people communicate. Other than cellular phone services, the wireless data communication has attracted great attention in recent years. In the transceiver design of a wireless LAN system, the low-power amplifier (LNA) plays an important role in the signal receiving path. It is required to provide sufficient signal amplification while maintaining a minimum noise to ensure the quality of the received signal. In this thesis, LNAs are designed and fabricated in a standard 0.18-μm CMOS technology for low-power and dual-band applications. The first CMOS LNA demonstrated is focused on its low-power and low-voltage operation. With a current-reused topology, the common-source gain stages are stacked for minimum power dissipation while achieving high small-signal gain. The fully integrated 5.7-GHz LNA exhibits 16.4-dB gain, 3.5-dB noise figure and 8-dB gain tuning range with good input and output return losses. The LNA consumes 3.2-mW dc power from a supply voltage of 1 volt. A gain/power quotient of 5.12 dB/mW is achieved in this work. Another LNA is designed to achieve dual-band operations with minimum hardware overhead. By switching the size and dc bias current of the input transistor, good input matching can be achieved. In addition, switched capacitors are used for the output matching at both frequency bands. Using the proposed design technique, a fully integrated 2.4-GHz/5.2-GHz dual-band LNA is presented. The fabricated LNA exhibits 10.1-dB gain and 2.9-dB noise figure at 2.4-GHz band, and 10.9-dB gain and 3.7-dB noise figure at 5.2-GHz band. Input and output return losses better than 10 dB are achieved at both frequency bands without external machining components.