Design of Broadband CMOS Circuits for UWB and High-Speed Wireline Receivers
Date Issued
2007
Date
2007
Author(s)
Liao, Chih-Fan
DOI
en-US
Abstract
The rapidly-growing demand for high-speed wireless connections and the tremendous increase of data volume transported over the Internet have stimulated interest in broadband RF circuits and systems. Concurrently, the continuous scaling of CMOS technology has opened the opportunity to integrate high-speed circuits operating at tens of gigahertz together with the large digital portion of modern communication systems. While recognizing the inevitable trend of broadband communication as well as the huge potential of CMOS technology, this dissertation targets on circuit techniques and design methodologies that facilitate the realization of broadband CMOS receivers for high-speed wireless/wireline applications.
First of all, an ultra-wideband 3.1–10.6-GHz low-noise amplifier employing a broadband noise-canceling technique is presented. By using the proposed circuit and design methodology, the noise from the matching device is greatly suppressed over the desired UWB band, while the noise from other devices performing noise cancellation is minimized by the systematic approach. Fabricated in a 0.18-μm CMOS process, the IC prototype achieves a power gain of 9.7 dB over a –3dB bandwidth of 1.2–11.9-GHz and a NF of 4.5–5.1 dB in the entire UWB band. It consumes 20 mW from a 1.8 V supply and occupies an area of only 0.59 mm2.
Next, a 10-Gb/s automatic gain control (AGC) amplifier implemented in 0.18μm CMOS technology is described. The circuit incorporates a linear-in-dB controlled variable gain amplifier (VGA) with 58dB tuning range, which is achieved by utilizing parasitic vertical BJTs to generate the exponential function. To operate at 10-Gb/s, capacitive and shunt-series inductive peaking techniques are applied to the gain stages following the VGA. For input swings from 18m to 1Vpp per side, the differential output swing is 430mVpp within +0.4 to –0.8dB variation. The measured dynamic range is 35dB with BER< 10–12. The circuit consumes 54mW from a 1.8V supply excluding the output buffer.
As everyone knows, high-speed front-end amplifiers and CDR circuits play critical roles in broadband data receivers as the former needs to perform amplification at high data rate and the latter has to retime the data with the extracted low-jitter clock. The following chapter presents the design and experimental results of 40-Gb/s transimpedance-AGC amplifier and CDR circuit. The transimpedance amplifier incorporates reversed tripe-resonance networks (RTRNs) and negative feedback in a common-gate configuration. A mathematical model is derived to facilitate the design and analysis of the RTRN, showing that the bandwidth is extended by a larger factor compared to using the shunt-series peaking technique, especially in cases when the parasitic capacitance is dominated by the next stage. Operating at 40-Gb/s, the amplifier provides an overall gain of 2kΩ and a differential output swing of 520mVpp for input spanning from 440µApp to 4mApp, with BER< 10–9. The measured integrated input- referred noise is 3.3µArms. The half-rate CDR circuit employs a direction-determined rotary- wave quadrature VCO to solve the bidirectional-rotation problem in conventional rotary-wave oscillators. This guarantees the phase sequence while negligibly affects the phase noise. With 40-Gb/s 231–1 PRBS input, the recovered clock jitter is 0.7psrms and 5.6pspp. The retimed data exhibits 13.3pspp jitter with BER< 10–9. Fabricated in 90nm digital CMOS technology, the overall amplifier consumes 75mW and the CDR circuit consumes 48mW excluding the output buffers, all from a 1.2V supply.
Finally, a 40-Gb/s serial-link receiver including an adaptive equalizer and a CDR circuit is presented. A parallel-path equalizing filter is used to compensate the high-frequency loss in copper cables. The adaptation is performed by only varying the gain in the high-pass path, which allows a single loop for proper control and completely removes the RC filters used for separately extracting the high- and low-frequency content of the signal. A full-rate bang-bang phase detector with only 5 latches is proposed in the following CDR circuit. Minimizing the number of latches saves the power consumption and the area occupied by inductors while improving the performance by avoiding complicated routing of high-frequency signals. The receiver is able to recover 40-Gb/s data passing through a 4m cable with 10dB loss at 20-GHz. For an input PRBS of 27–1, the recovered clock jitter is 0.3psrms and 4.3pspp. The retimed data exhibits 500mVpp output swing and 9.6pspp jitter with BER< 10–12. Fabricated in 90nm CMOS technology, the receiver consumes 115mW, of which 58mW is dissipated in the equalizer and 57mW in the CDR.
Subjects
寬頻
超寬頻
broadband
CMOS
UWB
high-speed
Type
thesis
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