A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications

Resource

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Journal

IEEE International Symposium on Circuits and Systems

Pages

1074-1077

Date Issued

2005

Author(s)

Wey, I.-C.

Chang, L.-H.

Chen, Y.-G.

Chang, S.-H.

DOI

URI

Type

conference paper

File(s)

Name

01464778.pdf

Size

516.27 KB

Format

Adobe PDF

Checksum

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